The present invention relates to a semiconductor design technology, and more particularly, to an internal supply voltage generating circuit for generating an internal supply voltage using an external supply voltage and a method for generating an internal supply voltage.
In general, a semiconductor device such as a Double Data Rate Synchronous DRAM (DDR SDRAM) includes an internal supply voltage generating circuit. The semiconductor device effectively consumes power and stably operates using various levels of internal supply voltages generated from the internal supply voltage generating circuit. The internal supply voltage includes at least a core voltage generated by down-converting an external voltage and a pumping voltage and a substrate bias voltage that are generated by pumping an external supply voltage.
As semiconductor devices have become more highly integrated, internal circuit of semiconductor devices have been designed at the level smaller than sub-micron level in the dimension. While operation frequencies have been increasing, levels of external supply voltages have been decreasing. Therefore, attempts have been made to generate a stable internal supply voltage by using low external supply voltages.
FIG. 1 is a diagram illustrating an internal supply voltage generating circuit according to prior art.
Referring to FIG. 1, the internal supply voltage generating circuit includes a voltage comparator 110 and a driver 130.
The voltage comparator 110 compares a level of a reference voltage V_REF with a level of an internal supply voltage V_INT. In general, the voltage comparator 110 uses a differential amplifier and includes a first input terminal for receiving a reference voltage V_REF and a second input terminal for receiving an internal supply voltage V_INT.
The driver 130 drives a terminal of an internal supply voltage V_INT in response to an output signal of the voltage comparator 110. The driver 130 includes a PMOS transistor PM, a resistor R, and a capacitor C. The PMOS transistor PM forms a source-drain path between an external supply VDD and a terminal of the internal supply voltage V_INT and a gate for receiving an output signal of the voltage comparator 110. The resistor R and the capacitor C is connected between the terminal of the internal voltage supply voltage V_INT and a ground VSS in parallel.
Hereafter, operations of an internal supply voltage generating circuit according to prior art will be described.
When a semiconductor device is operated, a level of an internal supply voltage V_INT is initially lower than that of a reference voltage V_REF. Therefore, the voltage comparator 110 generates a low output signal (that is, the ground VSS). The PMOS transistor PM of the driver 130 is turned on in response to the output signal of the voltage comparator 110 and performs a pull-up operation to pull up a level of the internal supply voltage V_INT to a level corresponding to or at least substantially equal to the external supply voltage VDD. The pull-up operation gradually increases the level of the internal supply voltage V_INT. Such an increased internal supply voltage V_INT is fed back to the voltage comparator 110. The voltage comparator 110 compares the feed-back voltage (that is, internal supply voltage V_INT) with the reference voltage V_REF again. If the level of the internal supply voltage V_INT is higher than that of the reference voltage V_REF, the voltage comparator 110 outputs a high output signal that turns off the PMOS transistor PM. Accordingly, the external supply VDD is stopped from being supplied to the terminal of internal supply voltage V_INT. Thus, when the internal supply voltage (V_INT) reaches a high level, the pull-up operation is stopped.
Meanwhile, a level of the internal supply voltage V_INT may fluctuate in response to power drawn off the terminal of the internal supply voltage V_INT due to operations of the semiconductor device. For example, although the internal supply voltage V_INT is sustained at a level corresponding to or at least substantially equal to the reference voltage V_REF in an operation period, the level of the internal supply voltage V_INT may be lower than the reference voltage V_REF in another operation period in response to power drawn off the terminal of the internal supply voltage V_INT. In this case, the internal supply voltage V_INT can restore a voltage level corresponding to or at least substantially equal to the reference voltage V_REF through the above described operations. A required time for restoring the level of the internal supply voltage V_INT to the level of the reference voltage V_REF after the level of the internal voltage V_INT becomes lower (or higher) than the level of the reference voltage V_REF is referred to as a response time.
Here, the response time corresponds to a response speed of each component within the internal supply voltage generating circuit. That is, a faster response speed of each component means a faster response time. While the response time is not major factor for a semiconductor device having a comparatively low operation frequency, the response time becomes a major factor in a semiconductor device having a comparatively high operation frequency. If the response time is not fit for maintaining the required operation frequency of the semiconductor device, an internal supply voltage V_INT corresponding to or at least substantially equal to the reference voltage V_REF may not be generated within a desired time. Thus, an internal circuit operating at a high operation frequency may not receive a stable internal supply voltage V_INT within a desired time.
Meanwhile, the internal supply voltage generating circuit in FIG. 1 according to prior art has a slow response time due to the below-stated reasons.
First, the PMOS transistor PM of the driver 130 is used to drive the terminal of the internal supply voltage V_INT. Since the terminal of the internal supply voltage V_INT supplies power to other circuits, the PMOS transistor PM is generally designed to have a big size. That is, a capacitance value of the PMOS transistor PM is large compared to that of the voltage comparator 110. Also, a resistor R having a great resistance value is used in order to make a gain of the voltage comparator 110 comparatively large. The above-described large capacitance value of the PMOS transistor PM and the large resistance value of the resistor R make the response speed of the voltage comparator 110 through the PMOS transistor PM and the resistor R to be slow. Such a slow response speed of the voltage comparator 110 slows down the response time of the internal supply voltage V_INT in compensating a voltage decrease (or increase) in the internal supply voltage V-INT.
Due to such a slow response time of prior internal supply voltage generating circuits in compensating a voltage decrease (or increase) in the internal supply voltage VINT, instable internal supply voltage V_INT may be applied to internal circuits of a semiconductor device. Such an instable internal supply voltage often causes errors in semiconductor devices.